BladeRF 2.0 micro xA9 SDR transceiver 47 MHz-6 GHz 301 CLE FPGA

54900,00  UAH.

⚠ All prices include VAT

BladeRF 2.0 micro xA9 Next-generation Software-Defined Radio (SDR) with a frequency range of 47 MHz to 6 GHz, 2×2 MIMO, FPGA with 301K logic elements

SKU: BRFM-XA9 Categories: ,
BladeRF 2.0 micro xA9 SDR transceiver 47 MHz-6 GHz 301 CLE FPGA

Delivery methods

Nova Poshta or pickup from our warehouse

BladeRF 2.0 micro xA9 SDR transceiver 47 MHz-6 GHz 301 CLE FPGA

Payment method

Bank transfer to our current account

BladeRF 2.0 micro xA9 SDR transceiver 47 MHz-6 GHz 301 CLE FPGA

Guarantee

12 months, exchange/return of goods within 14 days, in accordance with current legislation

Description

Description

bladeRF 2.0 micro xA9 is a next-generation software-defined radio (SDR) with a frequency range of 47 MHz to 6 GHz, a sampling frequency of 61,44 MHz (up to 122,88 MHz) and 2×2 MIMO streaming. Packaged in a small form factor, the bladeRF 2.0 micro was designed for high performance and mobile applications. Thanks to libbladeRF, bladeRF 2.0 micro is compatible with GNURadio, GQRX, SDR-Radio, SDR#, gr-phosphor, SoapySDR, and others. under Windows, Linux and macOS.

A shielding shroud protects sensitive RF components from electromagnetic interference (EMI) and provides additional heat dissipation, allowing the bladeRF 2.0 micro to operate in harsh environments.

All RF SMA ports are capable of powering wideband amplifiers and preamplifiers using a current injector scheme. The power supply of peripheral devices with a current injector is controlled by software, which provides maximum operational flexibility.

The bladeRF 2.0 micro xA9 features the largest-in-class 301KLE Cyclone V FPGA, which is a critical component for hardware accelerators and HDL signal processing circuits, including FFTs, turbo decoders, transmit modulators/filters, and receive correlators for packet modems. The 301KLE xA9 FPGA has significantly more FPGA space than the xA4 for similar applications. The BladeRF does not ship with these (or any) accelerators or processing circuits, and it is entirely up to the end customer to design or purchase them from third-party vendors.

Improved clock generator

The advanced synchronization architecture allows the bladeRF 2.0 micro to receive and transmit a 38,4 MHz clock signal from other devices. In addition, the built-in PLL circuit allows the bladeRF 2.0 microcontroller to synchronize the built-in clock with an external 10 MHz reference signal. The xA9 model uses a high-precision, stable clock generator. The built-in DAC controls the frequency tuning adjustment of the generator for factory calibration.

The power circuits of the bladeRF 2.0 micro module are a complex combination of low-noise and high-efficiency pulse and linear power regulators. Although the bladeRF 2.0 micro can be powered solely from the USB bus, an external power supply must be connected to ensure maximum linearity for current injector powered peripherals. The power circuits feature automatic switching circuitry to optimize power consumption between the USB bus and external DC power.

The bladeRF 2.0 micro module can operate in an unmanaged standalone mode without requiring a connection to an external controller or computer. The volume of the built-in flash memory is large enough to accommodate a FPGA image of any xA9 size.

Features and functions

Additional information
Brand
FPGA size301 CLE
Files
PDF
bladeRF Block diagram and electrical diagram
bladerf-2.0-micro-rev1.4.pdf • 9.91 Mb
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